Unidirectional configurations always have:

• 1 Master → 1 Slave direction
• 1 Clock Lane, always forward (Master → Slave)
• 1 or more Unidirectional Data Lanes, also forward-only
• No reverse communication (unless LPDT is optionally added)

Three main setups exist:

Single Unidirectional Data Lane

One Clock Lane + One Data Lane (Forward Only)

This is the simplest D-PHY link:
Clock Lane: Master → Slave Data Lane: Master → Slave

• Communication is only forward.
• No LPDT in the example.
• Requires 4 wires:
  • 2 wires for the Clock Lane (differential)
  • 2 wires for the Data Lane (differential)

Diagram description

• On the left: Master with a Clock Lane module + a Data Lane module
• On the right: Slave with corresponding lane modules
• Each lane connects point-to-point

Multiple Unidirectional Data Lanes

One Clock Lane + N Data Lanes → Higher Bandwidth

Clock Lane: Master → Slave Data Lane 0..N-1: Master → Slave

• Still forward-only communication.
• Used when higher throughput is needed.
• The protocol layer can activate Data Lanes independently.
• With N Data Lanes:
  • Total wires = 2 × (N + 1)
    (each lane uses a differential pair)

Example

For N=3 lanes:

• 1 Clock Lane
• 3 Data Lanes
  = 1 + 3 = 4 differential pairs → 8 wires

Dual-Simplex Configuration (Two Independent Unidirectional PHYs)

Two Directions, but Built from Two Separate Unidirectional Links

This configuration uses:

• A forward-only PHY (Master → Slave)
• A reverse-only PHY (Slave → Master)

Each direction has:

• Its own Clock Lane
• One or more Data Lanes
• Its own Master/Slave relationship